鐢熸垚寮忎汉宸ユ櫤鑳藉揩閫熷彂灞曞绠楀姏涓庡瓨鍔涘憟鎸囨暟闇€姹傚闀匡紝杩涗竴姝ュ姞鍓т簡绠楀姏涓庡瓨鍔涗箣闂存棦鏈夌煕鐩撅紝鏃朵唬鍦ㄥ懠鍞ゆ洿澶х殑杩愬姏锛堝嵆璁$畻涓庡瓨鍌ㄤ箣闂寸殑鏁版嵁浼犺緭锛?-AIGC鏃朵唬闇€瑕佹洿澶у甫瀹斤紝鏇翠负蹇€熺殑鏁版嵁浼犺緭璺緞銆?/span>
浼楁墍鍛ㄧ煡锛孭CIE鏄洰鍓嶆墍鐭ユ渶涓哄父瑙佺殑楂樻€ц兘I/O閫氫俊鍗忚锛屼絾鍙楅檺浜嶱CIE鎬荤嚎鐨?/span>鏍戝舰鎷撴墤浠ュ強鏈夐檺鐨勮澶囨爣璇咺D鍙风爜鑼冨洿锛岃嚧浣垮叾鏃犳硶褰㈡垚涓€涓ぇ瑙勬ā缃戠粶銆傚挨鍏跺湪NVMe澶ц妯′娇鐢ㄦ椂鍗犵敤澶ч噺鐨凱CIe绾胯矾锛屼娇鍏跺師鏈氨涓虹揣寮犵殑閫氶亾鏇存樉鎹夎瑙佽倶锛屽悓鏃朵篃闄愬埗浜咷PU銆丯IC銆丗PGA/ASIC鍗$殑鎺ュ叆鏁伴噺銆傚敖绠″彲浠ヤ娇鐢≒CIe Switch鏉ョ紦瑙i€氶亾鏁伴噺涓嶅鐨勯棶棰橈紝瀵逛簬PCIE鎬荤嚎璁惧ID鍙风殑涓嶈冻锛孭CIE Switch骞舵病鏈夊彲浠ヤ竴鍔虫案閫哥殑瑙e喅鏂规銆?/span>

闄ゆ涔嬪锛孭CIE鐨勮璁¤繕瀛樺湪涓や釜鑷村懡鐨勭己闄凤細瀛樺偍鍣ㄥ湴鍧€绌洪棿闅旂銆佷笉鏀寔Cache Coherency浜嬪姟銆侾CIE鍘熸湰璁捐鍒濊》鏄湴鍧€绌洪棿鏄鏈夌殑锛屽畠涓庡師鏈夌殑CPU鍦板潃绌洪棿涓嶇浉铻嶅悎锛岄渶瑕佸€熷姪鍦板潃缈昏瘧瀵勫瓨鍣ㄦ潵鍋氬熀鍦板潃缈昏瘧銆傚敖绠¤繖骞朵笉褰卞搷CPU涓嶱CIE浜掔浉璁块棶鍦板潃涓殑鏁版嵁锛屼絾鐢变簬PCIE浜嬪姟灞備笉鏀寔Cache Cohernecy浜嬪姟鐨勫鐞嗭紝鍥犳PCIE璁惧绔棤娉曠紦瀛楥PU鍦板潃鍩熶腑鐨勬暟鎹紝杩欑洿鎺ュ鑷存暟鎹€氫俊鏃剁殑寤惰繜銆?/span>
涓轰簡瑙e喅涓婅堪闂锛岃嫳鐗瑰皵鍦?019骞磋仈鍚堜笟鐣屾帹鍑轰簡Compute Express Link锛圕XL鎶€鏈崗璁級鐢ㄤ互鍔犻€烠PU涓嶨PU浠ュ強FPGA绛夊紓鏋勭粨鏋勪箣闂寸殑浜掕仈閫氫俊銆傛€荤殑璇存潵锛孋XL鍩轰簬PCIE鎶€鏈紝閫氳繃灏嗚澶囨寕杞藉埌PCIe鎬荤嚎涓婏紝瀹炵幇浜嗚澶囧埌CPU涔嬮棿鐨勪簰鑱斻€侰XL鍙互瑙嗕负PCIE鎶€鏈殑鍗囩骇鐗堟湰锛屽洜姝ゅ畠鍏煎鐜版湁PCIe绔彛鐨勫鐞嗗櫒锛堢粷澶ч儴鍒嗙殑閫氱敤CPU銆丟PU 鍜?FPGA锛夈€?/span>CXL 閫氳繃灏嗚绠楀拰瀛樺偍鍒嗙锛屽舰鎴愬唴瀛樻睜锛屼粠鑰岃兘鍔ㄦ€佹寜闇€閰嶇疆鍐呭瓨璧勬簮锛屾彁鍗囨暟鎹腑蹇冨伐浣滄晥鐜囥€?/span>CXL浣滀负涓€绉嶆柊鍑虹幇鐨勬妧鏈紝鍑犱箮涓€骞翠竴娆℃洿鏂般€?/span>
鍦–XL1.0鐨勬妧鏈熀纭€涓婏紝CXL2.0澧炲姞浜嗕竴涓噸瑕佺殑鍔熻兘锛氬畠鎴愬姛瀹炵幇浜嗗唴瀛樿祫婧愮殑姹犲寲銆傞€氫俊鐡堕鐨勯棶棰樼敱鏉ュ凡涔咃紝闅忕潃NVMe纭洏鐨勬帹鍑猴紝杩熷欢寰楀埌澶у箙搴﹂檷浣庯紝浣嗘槸鍚炲悙渚濈劧鏄緢鏄庢樉鐨勭己闄凤紝鍥犳骞朵笉鑳藉畬鍏ㄦ浛浠e唴瀛橈紝闅忕潃AI/ML绛夊楂橀€烮/O鐨勯渶姹傦紝鍥犳姹犲寲鎴愪负浜嗘渶浣抽€夋嫨銆侰XL2.0鐨勬灦鏋勬敮鎸丮emory sharing鎶€鏈紝鑰岃繖绉嶆妧鏈垚鍔熺獊鐮翠簡鏌愪竴涓?/span>鐗╃悊鍐呭瓨鍙兘灞炰簬鏌愪竴鍙版湇鍔″櫒鐨勯檺鍒讹紝鍦ㄧ‖浠朵笂瀹炵幇浜嗗鏈哄叡鍚岃闂悓鏍峰唴瀛樺湴鍧€鐨勮兘鍔涳紝鑳藉璺ㄧ郴缁熻澶囧疄鐜拌祫婧愬叡浜€傜洰鍓岰XL宸茬粡鍗囩骇鍒颁簡3.0鐗堟湰锛屽甫瀹芥彁鍗囦簡涓ゅ€嶏紝鏀寔鏇村鏉傜殑杩炴帴鎷撴墤锛屽閫氳繃瀹冧娇澶氫釜Switch浜掔浉杩炴帴锛屽彲浠ュ疄鐜颁笂鐧句釜鏈嶅姟鍣ㄤ簰鑱斿苟鍏变韩鍐呭瓨銆?/span>
鑰孏en-Z鍒欐槸闄や簡CXL浜掕仈鎶€鏈箣澶栵紝鍦ㄦ暟鎹腑蹇冦€侀珮鎬ц兘璁$畻棰嗗煙銆丄I棰嗗煙绛夊満鏅殑鍏ㄦ柊鏁版嵁璁惧浜掕仈鍗忚鐨勫彟涓€缁熸不鑰呫€侴en-Z鐨勫嚭鐜颁富瑕佹槸涓轰簡寮ヨˉCXL鍦ㄦ湇鍔″櫒鑺傜偣澶栭儴鐨勬満鏋跺眰绾э紝杩滆窛绂讳紶杈撳拰澶ц妯℃嫇鎵戜簰鑱斿満鏅殑缂洪櫡銆傚€煎緱涓€鎻愮殑鏄紝鍦?022骞碐en-Z 鑱旂洘鍚屾剰鎺ュ叆CXL 鎶€鏈崗璁紝涓や釜鑱旂洘瀹炵幇浜嗗崗璁吋瀹广€?/span>
鑻变紵杈句篃鎺ㄥ嚭浜嗗叾鑷富鐮斿彂鐨?/span>NVLink鎶€鏈紝NVLink鍚屾牱鎻愪緵楂樺甫瀹斤紝閫傜敤浜庤繛鎺VIDIA GPU銆侼VLink涔熸敮鎸丟PU涔嬮棿鐨勫唴瀛樺叡浜紝浼樺寲浜嗗ぇ瑙勬ā骞惰璁$畻鐨勬€ц兘锛屽湪GPU涔嬮棿鐨勯€氫俊涓叿鏈夋洿浣庣殑寤惰繜銆侼VLink鍙互鏀寔CPU-GPU闂撮摼璺篃鍙互鏀寔GPU-GPU闂撮摼璺€傞櫎姝や箣澶栵紝鑻变紵杈捐繕鐮斿彂浜嗚嚜宸辩殑 NVLink Switch锛屾敮鎸佹惌杞?6涓狦PU+NVLink Switch锛屼笉杩囦环鏍兼槀璐点€?/span>
CXL鎿呴暱浜庤绠楃浉鍏崇殑鏁版嵁澶勭悊锛屽鏁版嵁涓績銆佷汉宸ユ櫤鑳姐€佺瀛﹁绠楃瓑搴旂敤棰嗗煙锛屽叿澶囨洿楂樼殑鐏垫椿鎬т笌楂樻€ц兘锛岃€孨VLink涓昏鐢ㄤ簬杩炴帴NVIDIA GPU锛屽湪鍥惧舰澶勭悊鍜屾繁搴﹀涔犵瓑棰嗗煙琛ㄧ幇鍑鸿壊銆?/span>
鍏跺疄鍦ㄦ渶鍒濅负浜嗚В鍐?CPU 鍜岃澶囥€佽澶囧拰璁惧涔嬮棿鐨勫唴瀛橀缚娌燂紝IBM灏辩巼鍏堟帹鍑轰簡CAPI锛圕oherent Accelerator Processor Interface锛夋帴鍙o紝浣嗙敱浜嶪BM鍦ㄦ暟鎹腑蹇冭澶囧崰姣旂巼浣庝笌鏃ユ笎寮忓井鐨勫奖鍝嶅姏锛孋API骞舵病鏈夊緱鍒板ぇ瑙勬ā鐨勪娇鐢紝鑰屽悗鍙堟紨鍙樹簡閫愭笎婕斿寲鎴愪簡OpenCAPI銆傝€屽悗ARM鍙?/span>鍔犲叆鍙︿竴涓紑鏀剧殑璁垮瓨鍜孖/O缃戠粶骞冲彴锛圕CIX锛塁ache Coherent Interconnect for Accelerators銆傛€昏€岃█涔嬶紝鍦ㄧ爺鍙戞帹鍑虹殑鏃堕棿涓婏細CAPI->GenZ->CCIX->NVLINK->CXL銆?/span>
灏界瑙e喅澶勭悊鍣ㄤ笌鍐呭瓨涔嬮棿閫氳鐡堕涔嬭矾姘告棤姝㈠锛屼絾鎴戜滑鍙互娓呮櫚棰勮鍦ㄤ笉杩滅殑灏嗘潵锛岄殢鐫€CXL鎶€鏈殑鍙戝睍锛屽唴瀛樿祫婧愬交搴曟睜鍖栵紝鏈嶅姟鍣ㄧ殑澶栬褰㈡€佸皢浼氬彂鐢熸牴鏈殑鍙樺寲锛屽瓨鍌ㄥ拰澶勭悊鍣ㄤ細琚垎绂诲紑鏉ワ紝鏀惧湪褰兼鐙珛鐨勬満绠卞唴銆?/span>
鐩稿叧鎺ㄨ崘
2026-06-01
閭€璇峰嚱涓℅ooxi 璇氶個鎮ㄥ叡璧?COMPUTEX 2026锛屽姪鏁板瓧缁忔祹鑵鹃
2026-04-30
澶фā鍨嬫妧鏈穬杩侊紝鍥介懌绠楀姏鎵樺簳
2025-12-19
寮鸿姱鑱氱畻锛屽崗鍚岃繘鍖栵細鍥介懌涓庢矏鏇﹀叡绛戝浗浜I绠楀姏鏂扮敓鎬?/p>
2025-11-21
鍙峰锛氱畻鍔涚璧佸競鍦衡€滄€ц兘鐜嬧€濆凡灏变綅锛岄噸鏂板畾涔夋€т环姣旀爣鏉?/p>
2025-10-23
绠楀姏璧嬭兘锛屾櫤瑙佹湭鏉ワ細鍥介懌浜浉ICG-20锛屽叡璧寸粍瀛︿笌AI鏂扮邯鍏?/p>
2023-07-20
绮ゆ腐婢冲ぇ婀惧尯AI+淇℃伅瀹夊叏浜т笟鐮旇浼氭毃涔﹁甯﹂槦鏈嶅姟浼佷笟鈥斿浗閼亽杩愭椿鍔ㄦ垚鍔熶妇鍔?/p>